File:5 Stage Pipeline.svg
此 SVG 檔案的 PNG 預覽的大小：300 × 190 像素。 其他解析度：320 × 203 像素 | 640 × 405 像素 | 1,024 × 649 像素 | 1,280 × 811 像素 | 2,560 × 1,621 像素。
原始檔案 （SVG 檔案，表面大小：300 × 190 像素，檔案大小：33 KB）
| 描述 |
English: A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, the third in the "instruction decode" phase, the fourth in the "instruction fetch" phase and the fifth hasn't been fetched yet. |
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| 日期 | |||
| 來源 | 自己的作品 | ||
| 作者 | Inductiveload | ||
| 授權許可 (重用此檔案) |
|
 | This SVG image was uploaded in a graphics format such as GIF, PNG, JPEG, or SVG. However, it consists purely or largely of information which is better suited to representation in wikitext (possibly using MediaWiki's special syntax for tables, math, or music). This will make the information easier to edit, as well as make it accessible to users of screen readers and text-based browsers.
If possible, please replace any inclusions of this image in articles (noted under the “File links” header) with properly formatted wikitext. After doing so, please consider nominating this image for deletion. |  |
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| 日期/時間 | 縮圖 | 尺寸 | 使用者 | 備註 | |
|---|---|---|---|---|---|
| 目前 | 2009年1月22日 (四) 18:24 | | 300 × 190（33 KB） | Inductiveload | {{Information |Description={{en|1=A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, t |
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